Meet Adler Lake, a first performance hybrid architecture as Intel’s next-generation architecture, that was introduced on the commemoration of Structure Day 2021.

Adler Lake, according to Intel, combines an Efficiency-core and an Eco-core to provide critical efficiency across all workload types.

On the occasion of Structural Day 2021, Adler Lake showcased new architectural inventions in the hardware sector.

As Intel's first hybrid big.LITTLE design for desktops, Alder Lake signifies a fundamental shift in how CPUs are put together. It is said to be the first desktop processor to employ Intel's 7 manufacturing process, which was previously known as the 10nm Enhanced SuperFin process until Intel's naming strategy was realigned with that of other chip manufacturers.

Intel worked on and improved the Intel Thread Director to make the cores work in unison with the rest of the computer. According to Intel, the Thread Director is built directly into the core and is designed to ensure that the working machine places the right thread at the correct core at the correct time.

Intel also detailed its two new x86 central processing unit architectures, as well as its next-generation data center processors, infrastructure processing unit architectures, and forthcoming graphics architectures.

Adler Lake will deliver efficiency and scalability to boost all consumer categories, from ultra-portable laptops to business desktops, according to the chipmaker.

The 12th-generation Adler Lake chips, like their predecessors, will use ARM's BIG.little technology, which is a combination of high-performance and high-efficiency cores.

Adler Lake is claimed to be based on an upgraded version of the 10nm SuperFin technology, which will compete with Apple's ARM instruction set, which was utilized in the M1. This, together with Intel's BIG.little architecture, confirms the company's desire to compete with Apple's processor.

In contrast to its predecessor Rocket Lake, Adler Laker appears to prioritize power efficiency over performance, combining high-performance cores with high-efficiency cores into a single device. As long as the remainder of the semiconductor is not changed, the latter could result in significant increases in battery life.

Alder Lake is also rumored to support PCIe Express Generations 4 and 5, Thunderbolt 4, and DDR4/DDR5 memory.

Intel announced two infrastructure processing unit structures, known as IPUs which are Mount Evans and Oak Springs Canyon. Mount Evans is the chipmaker's first ASIC IPU, designed for advanced and scattered data centers, whereas Oak Springs Canyon is an IPU reference platform built using the company's Xeon D CPU and the Agilex FPGA. The IPU's purpose is to reduce overhead and increase efficiency for central processing units.