NITI Aayog has established an ambitious goal of creating a $ 120-150 billion semiconductor value chain by 2035, presenting a 10-year plan designed to elevate India into a crucial participant in the global chip ecosystem.

In a significant effort to enhance India's electronics manufacturing presence and ensure technological independence, NITI Aayog's Frontier Tech Hub unveiled the strategic document called “Future of India’s Semiconductor Industry” in May 2026.

The report presents a stepwise plan to transition India from a downstream consumer of semiconductors to an essential hub in the global value chain.

The roadmap follows closely after the Union Budget 2026 announcement of ISM 2.0 (India Semiconductor Mission), indicating a strategic transition from building an ecosystem to enhancing and expanding capabilities.

Instead of directly competing in the pursuit of advanced foundry nodes, the report endorses a distinct “More-than-Moore” approach that capitalizes on India’s advantages in chip design and targets rapidly expanding niche markets.

The report forecasts that by 2035, India may secure 10-13percent of the worldwide semiconductor market, which would bolster a local semiconductor market worth almost $ 200 billion. It also aims for 35-50percent self-sufficiency in semiconductor demand and seeks to keep 55-70percent of value capture domestically through local design, packaging, and materials ecosystems.

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India seeks to become one of the leading three global hubs for Outsourced Semiconductor Assembly and Test (OSAT) and advanced packaging, while establishing a strong presence in AI, quantum computing, and high-performance computing chip design, possessing over 100 advanced intellectual properties (IPs).

Ashok Kumar Lahiri, Vice Chairman of NITI Aayog, stated that increasing reliance on foreign black-box technologies presents a significant strategic threat to the Viksit Bharat vision, emphasizing that technological sovereignty should start at the infrastructure level.

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The strategy revolves around five main pillars — Pioneering, Policy and Investment, Production, People, and Partnership — aimed at addressing structural issues like capital intensity, workforce shortages, and lengthy development timelines.

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Within the Pioneering pillar, the report suggests graduated subsidies for Electronic Design Automation (EDA) tools, a National Design and Packaging Co-Design Platform, and an AI-driven Semiconductor Engineering Mission focused on reducing chip design cycles via agentic AI.