Samsung, SK hynix Unveil Next-Gen Memory Beyond HBM
Samsung Electronics and SK hynix are taking steps to bring to market a new type of memory that incorporates an additional layer for artificial intelligence systems, as the industry reaches the thresholds of merely stacking more high-bandwidth memory alongside the chips requiring it.
Both firms are creating products utilizing the latest version of Compute Express Link, or CXL, a standard that links processors and memory through the shared PCIe interface. It fits between traditional DRAM and solid-state storage, providing significantly more capacity than the memory connected directly to a chip while remaining sufficiently quick for use in real-time processing.
SK hynix demonstrated the progress it has made at HPE's Discover conference held in Las Vegas in June. It showcased a second-generation 256-gigabyte CMM-DDR5 prototype utilizing CXL 3.2, doubling the capacity of its first-generation version, operating in a pooled-memory server from the AI infrastructure company Liqid. A schedule for production has yet to be established.
Samsung is reportedly targeting year-end for the production of its next-gen CMM-D module, though earlier reports in July suggested the schedule might extend to 2027 due to delays with the supporting server platforms, mainly Intel and AMD processors.
The company mentioned that "even with some modifications to elements of the plan," it is set to start production on time.
The drive indicates a transition in AI memory, moving from a competition focused on pure speed to one centered on the structure of the memory system. The main problem is capacity.
In present AI servers, HBM is positioned alongside the graphics processor, while standard DRAM is located next to the central processor; however, neither can be independently expanded as each is linked to its respective chip.
Increasing memory typically involves incorporating costly processors as well. CXL disrupts that reliance, allowing a system to access a vast memory pool without needing to purchase additional compute resources to store it. The demand has increased as AI operators struggle with the expenses and availability of GPUs.
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The urgency has intensified as AI transitions from developing models to deploying them broadly. Operating a large language model accumulates an increasing repository of session data, the key-value cache, and when that exceeds the available memory, systems experience slowdowns or repeat work that has already been completed.
Both creators have shifted to reveal the benefits. In a test conducted on July 9, Samsung reported that a 1-terabyte CXL memory pool achieved roughly 92 percent of DRAM-level inference performance across eight GPUs, while maintaining significantly larger caches compared to a traditional configuration.
Researchers from SK hynix reported a throughput increase of up to 35.7 percent by utilizing CXL as a shared terabyte-scale tier for inference in work published in June. Both numbers resulted from the companies' internal testing under particular circumstances.
Currently, the technology remains in its infancy, with the market anticipating server platforms and software to advance.
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However, the advantage is not guaranteed. CXL memory operates at a slower speed compared to local DRAM, and a significant part of its worth relies on software determining the placement of data across different tiers. This has positioned controllers, firmware, and memory-management tools as competitors alongside the chips.
Currently, the technology remains in its infancy, with the market anticipating server platforms and software to advance.
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"With the growth of AI, the market's demand for CXL will increase, significantly starting in 2026," stated Yim So-jung, an analyst at Eugene Investment & Securities. "By 2028, server platforms with CXL capability are expected to become mainstream."



